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data sheet 1 1999-09-15 2-phase stepper-motor driver bipolar ic tle 4726 overview features ?2 0.75 a / 50 v outputs ? integrated driver, control logic and current control (chopper) ? fast free-wheeling diodes ? low standby-current drain ? full, half, quarter, mini step p-dso-24-3 description tle 4726 is a bipolar, monolithic ic for driving bipolar stepper motors, dc motors and other inductive loads that operate on constant current. the control logic and power output stages for two bipolar windings are integrated on a single chip which permits switched current control of motors with 0.75 a per phase at operating voltages up to 50 v. the direction and value of current are programmed for each phase via separate control inputs. a common oscillator generates the timing for the current control and turn-on with phase offset of the two output stages. the two output stages in a full-bridge configuration have integrated, fast free-wheeling diodes and are free of crossover current. the logic is supplied either separately with 5 v or taken from the motor supply voltage by way of a series resistor and an integrated z-diode. the device can be driven directly by a microprocessor with the possibility of all modes from full step through half step to mini step. type ordering code package tle 4726 g q67006-a9297 p-dso-24-3
tle 4726 data sheet 2 1999-09-15 figure 1 pin configuration (top view) q12 q22 q21 gnd gnd osc phase 1 phase 2 11 i r 1 iep00898 10 i gnd q11 v s ++ l v 2 r inhibit i 20 i 21 gnd 24 1 23 2 22 3 21 4 20 5 19 6 18 7 17 8 16 9 15 10 14 11 13 12 gnd gnd gnd gnd
tle 4726 data sheet 3 1999-09-15 pin definitions and functions pin no. function 1, 2, 23, 24 digital control inputs i x0, i x1 for the magnitude of the current of the particular phase. 3 input phase 1 ; controls the current through phase winding 1. on h-potential the phase current flows from q11 to q12, on l-potential in the reverse direction. 5, 6, 7, 8, 17, 18, 19, 20 ground ; all pins are connected internally. 4 oscillator ; works at approx. 25 khz if this pin is wired to ground across 2.2 nf. 10 resistor r 1 for sensing the current in phase 1. 9, 12 push-pull outputs q11, q12 for phase 1 with integrated free-wheeling diodes. 11 supply voltage ; block to ground, as close as possible to the ic, with a stable electrolytic capacitor of at least 10 m f in parallel with a ceramic capacitor of 220 nf. 14 logic supply voltage ; either supply with 5 v or connect to + v s across a series resistor. a z-diode of approx. 7 v is integrated. in both cases block to ground directly on the ic with a stable electrolytic capacitor of 10 m f in parallel with a ceramic capacitor of 100 nf. 13, 16 push-pull outputs q22, q21 for phase 2 with integrated free-wheeling diodes. 15 resistor r 2 for sensing the current in phase 2. 21 inhibit input ; the ic can be put on standby by low potential on this pin. this reduces the current consumption substantially. 22 input phase 2 ; controls the current flow through phase winding 2. on h-potential the phase current flows from q21 to q22, on l potential in the reverse direction. i x1 i x0 phase current example of motor status h h 0 no current h l 1/3 i max hold l h 2/3 i max set ll i max accelerate typical i max with r sense = 1 w: 750 ma
tle 4726 data sheet 4 1999-09-15 figure 2 block diagram ieb00899 d14 d13 d12 d11 t14 t12 t13 t11 14 11 9 12 10 q11 q12 r 1 4 1 2 3 oscillator functional logic + v ls v + i 11 gnd phase 1 phase 1 phase 1 5-8, 17-19 phase 2 phase 2 phase 2 logic functional inhibit 22 23 24 21 2 r q22 q21 15 13 16 t21 t23 t22 t24 d21 d22 d23 d24 inhibit 10 i i 20 i 21
tle 4726 data sheet 5 1999-09-15 note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. absolute maximum ratings t a = C 40 to 125 c parameter symbol limit values unit remarks min. max. supply voltage v s 052vC logic supply voltage v l 0 6.5 v z-diode z-current of v l i l C50maC output current i q C 1 1 a C ground current i gnd C 2 2 a C logic inputs v ixx C 6 v l + 0.3 v i xx ; phase 1, 2; inhibit r 1 , r 2 , oscillator input voltage v rx, v osc C 0.3 v l + 0.3 vC junction temperature t j t j C C 125 150 c c C max. 10,000 h storage temperature t stg C 50 125 cC
tle 4726 data sheet 6 1999-09-15 note: in the operating range, the functions given in the circuit description are fulfilled. operating range parameter symbol limit values unit remarks min. max. supply voltage v s 550vC logic supply voltage v l 4.5 6.5 v without series resistor case temperature t c C 25 110 c measured on pin 5 p diss = 2 w output current i q C 800 800 ma C logic inputs v ixx C 5 v l v i xx ; phase 1, 2; inhibit thermal resistances junction ambient junction ambient (soldered on a 35 m m thick 20 cm 2 pc boar copper area) junction case r th ja r th ja r th jc C C C 75 50 15 k/w k/w k/w p-dso-24-3 p-dso-24-3 measured on pin 5 p-dso-24-3 characteristics v s = 40 v; v l = 5 v; C 25 c t j 125 c parameter symbol limit values unit test condition min. typ. max. current consumption from + v s from + v s from + v l from + v l i s i s i l i l C C C C 0.2 16 1.7 18 0.5 20 3 25 ma ma ma ma v inh = l v inh = h i q1/2 = 0, i xx = l v inh = l v inh = h i q1/2 = 0, i xx = l
tle 4726 data sheet 7 1999-09-15 oscillator output charging current charging threshold discharging threshold frequency i osc v oscl v osch f osc C C C 18 110 1.3 2.3 25 C C C 40 m a v v khz C C C c osc = 2.2 nf phase current selection current limit threshold no current hold setpoint accelerate v sense n v sense h v sense s v sense a C 200 420 700 0 250 540 825 C 300 680 950 mv mv mv mv i x0 = h; i x1 = h i x0 = l; i x1 = h i x0 = h; i x1 = l i x0 = l; i x1 = l logic inputs ( i x1 ; i x0 ; phase x) threshold l-input current l-input current h-input current v i i il i il i ih 1.4 (h ? l) C 10 C 100 C C C C C 2.3 (l ? h) C C 10 v m a m a m a C v i = 1.4 v v i = 0 v v i = 5 v standby cutout (inhibit) threshold threshold hysteresis v inh (l ? h) v inh (h ? l) v inhhy 2 1.7 0.3 3 2.3 0.7 4 2.9 1.1 v v v C C C internal z-diode z-voltage v lz 6.5 7.4 8.2 v i l = 50 ma characteristics (contd) v s = 40 v; v l = 5 v; C 25 c t j 125 c parameter symbol limit values unit test condition min. typ. max.
tle 4726 data sheet 8 1999-09-15 note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a =25 c and the given supply voltage. power outputs diode transistor sink pair (d13, t13; d14, t14; d23, t23; d24, t24) saturation voltage saturation voltage reverse current forward voltage forward voltage v satl v satl i rl v fl v fl C C C C C 0.3 0.5 C 0.9 1 0.6 1 300 1.3 1.4 v v m a v v i q = C 0.5 a i q = C 0.75 a v q = 40 v i q = 0.5 a i q = 0.75 a diode transistor source pair (d11, t11; d12, t12; d21, t21; d22, t22) saturation voltage saturation voltage saturation voltage saturation voltage reverse current forward voltage forward voltage diode leakage current v satuc v satud v satuc v satud i ru v fu v fu i sl C C C C C C C C 0.9 0.3 1.1 0.5 C 1 1.1 1 1.2 0.7 1.4 1 300 1.3 1.4 2 v v v v m a v v ma i q = 0.5 a; charge i q = 0.5 a; discharge i q = 0.75 a; charge i q = 0.75 a; discharge v q = 0 v i q = C 0.5 a i q = C 0.75 a i f = C 0.75 a characteristics (contd) v s = 40 v; v l = 5 v; C 25 c t j 125 c parameter symbol limit values unit test condition min. typ. max.
tle 4726 data sheet 9 1999-09-15 quiescent current i s , i l versus supply voltage v s output current i qx versus junction temperature t j quiescent current i s , i l versus junction temperature t j operating condition: v l =5 v v inh =h c osc = 2.2 nf r sense =1 w load: l = 10 mh r = 2.4 w f phase = 50 hz mode: fullstep 0102030v50 0 10 20 30 40 ma i xx = h = l xx i j t = 25 c s i l i l i ied01655 v s i s , l i -25 0 25 50 75 100 c 150 j t qx i ied01657 0 200 800 400 600 ma -25 0 25 50 75 100 150 c ied01656 xx i = h = l i xx = 40v l i l i i s j t 0 10 40 20 i i s , 30 l ma v s
tle 4726 data sheet 10 1999-09-15 output saturation voltages v sat versus output current i q typical power dissipation p tot versus output current i q (non stepping) forward current i f of free-wheeling diodes versus forward voltages v f permissible power dissipation p tot versus case temperature t c 0 0 0.5 0.2 0.4 0.6 1.0 v 1.5 v f i f 0.8 a t j 1.0 = 25 c fl vv fu ied01167 p-dso-24 p-dip-20 measured at pin 5. ied01660 0 6 8 w tot p 12 100 -25 0 50 25 75 c 175 t c 10 4 2 125
tle 4726 data sheet 11 1999-09-15 input characteristics of i xx , phase x, inhibit oscillator frequency f osc versus junction temperature t j input current of inhibit versus junction temperature t j v l = 5v -6 -5 -2 3.9 2 6 ied01661 0.8 0.4 0 0.4 ma ixx i 0.8 v v ixx 0.2 0.6 0.6 0.2 15 20 25 30 khz -25 0 25 50 75 100 125 c 150 v s l v osz c = 40v = 5v = 2.2nf osc f j t ied01663
tle 4726 data sheet 12 1999-09-15 figure 3 test circuit figure 4 application circuit aes02301 1 2 3 21 24 23 22 14 11 9 12 16 13 415 10 gnd osc 5, 6, 7, 8 17, 18, 19, 20 r 1 1 w r 2 w 1 2.2 nf phase 1 phase 2 inhibit v l v s q11 q12 q21 q22 tle 4726 220 nf 100 m f 220 nf 100 m f i l i s i gnd i osc v osc i q i fu i r i ru satl - - v satu v fu v s - v i v i i i i i l h l h i 10 11 i i i 21 20 v fl - sense v v v sense aes02302 1 2 3 21 24 23 22 14 11 9 12 16 13 41510 gnd osc 5, 6, 7, 8 17, 18, 19, 20 r 1 1 w r 2 w 1 2.2 nf micro controller i 11 20 21 phase 1 phase 2 inhibit v l v s q11 q12 q21 q22 tle 4726 m 220 nf 100 m f +40 v +5 v 220 nf 100 m f 10 i i i
tle 4726 data sheet 13 1999-09-15 figure 5 full-step operation t ied01666 accelerate mode normal mode acc set l h l h l h i phase 1 i q1 i i i 10 11 set i i acc i set i acc i q2 i acc set i i 21 20 i h h l l l h phase 2 t t t t t t t
tle 4726 data sheet 14 1999-09-15 figure 6 half-step operation t t t t t t ied01667 t accelerate mode normal mode t 21 i 20 phase 2 i l l h h h l q2 i - - - i set acc i i set acc i acc i q1 i - phase 1 set i set i l acc i h 10 i 11 i h h l l
tle 4726 data sheet 15 1999-09-15 figure 7 quarter-step operation
tle 4726 data sheet 16 1999-09-15 figure 8 mini-step operation h l h l h l i set i hold i 10 i 11 phase 1 i q1 t ied01665 acc i set i i hold acc i i acc set i set hold acc hold i i i i i q2 l h h l l h i i 20 21 phase 2 t t t t t t t
tle 4726 data sheet 17 1999-09-15 figure 9 current control osc v 0 i gnd v q12 v s + 0 s + v v + s + v s t t v fu sat 1 v satu d v satu c v phase x phase x operating conditions: v r l s = 40 v = 10 mh = 20 ied01177 0 w 2.4 v 1.4 v 0 t t v q11 v q22 v q21 t t t v l = 5 v inhibit xx v v v phase x = h = l = h
tle 4726 data sheet 18 1999-09-15 figure 10 phase reversal and inhibit inhibit oscillator high imped. oscillator high imped. phase 1 phase changeover high impedance high impedance high impe- dance slow current decay fast current decay ied01178 i gnd v osc 2.3 v 1.3 v 0 l l i n 0 t v q11 satl v fu v v satu c satu d v fl v s v + phase 1 i fast current decay by inhibit slow current decay operating conditions: v s = 40 v v = 5 v i phase 1 l phase 1 r i 1x = 20 = l; v + s q12 v = 10 mh w 1x i = h t t t t t t
tle 4726 data sheet 19 1999-09-15 calculation of power dissipation the total power dissipation p tot is made up of saturation losses p sat (transistor saturation voltage and diode forward voltages), quiescent losses p q (quiescent current times supply voltage) and switching losses p s (turn-on / turn-off operations). the following equations give the power dissipation for chopper operation without phase reversal. this is the worst case, because full current flows for the entire time and switching losses occur in addition. p tot = 2 p sat + p q + 2 p s where p sat @ i n { v satl d + v fu (1 C d ) + v satuc d + v satud (1 C d ) } p q = i q v s + i l v l i n = nominal current (mean value) i q = quiescent current i d = reverse current during turn-on delay i r = peak reverse current t p = conducting time of chopper transistor t on = turn-on time t off = turn-off time t don = turn-on delay t doff = turn-off delay t = cycle duration d = duty cycle t p / t v satl = saturation voltage of sink transistor (t3, t4) v satuc = saturation voltage of source transistor (t1, t2) during charge cycle v satud = saturation voltage of source transistor (t1, t2) during discharge cycle v fu = forward voltage of free-wheeling diode (d1, d2) v s = supply voltage v l = logic supply voltage i l = current from logic supply p s v s t ------ i d t don 2 --------------------- - i d i r + t on 4 ----------------------------- - i n 2 ---- - t doff t off + ++ ?t y @
tle 4726 data sheet 20 1999-09-15 figure 11 figure 12 dx3 dx4 dx1 dx2 v s + tx3 tx1 tx4 tx2 l v sense sense r ies01179 iet01210 voltage and current at chopper transistor t d t on off t off t p t v satl v sfu v + i d i r i n turn-on turn-off + v fu s v t d on
tle 4726 data sheet 21 1999-09-15 application hints the tle 4726 is intended to drive both phases of a stepper motor. special care has been taken to provide high efficiency, robustness and to minimize external components. power supply the tle 4726 will work with supply voltages ranging from 5 v to 50 v at pin v s . as the circuit operates with chopper regulation of the current, interference generation problems can arise in some applications. therefore the power supply should be decoupled by a 0.22 m f ceramic capacitor located near the package. unstabilized supplies may even afford higher capacities. current sensing the current in the windings of the stepper motor is sensed by the voltage drop across r 1 and r 2 . depending on the selected current internal comparators will turn off the sink transistor as soon as the voltage drop reaches certain thresholds (typical 0 v, 0.25 v, 0.5 v and 0.75 v); ( r 1 , r 2 =1 w ). these thresholds are neither affected by variations of v l nor by variations of v s. due to chopper control fast current rises (up to 10 a/ m s) will occur at the sensing resistors r 1 and r 2 . to prevent malfunction of the current sensing mechanism r 1 and r 2 should be pure ohmic. the resistors should be wired to gnd as directly as possible. capacitive loads such as long cables (with high wire to wire capacity) to the motor should be avoided for the same reason. synchronizing several choppers in some applications synchrone chopping of several stepper motor drivers may be desireable to reduce acoustic interference. this can be done by forcing the oscillator of the tle 4726 by a pulse generator overdriving the oscillator loading currents (approximately 100 m a). in these applications low level should be between 0 v and 1 v while high level should be between 2.6 v and v l . optimizing noise immunity unused inputs should always be wired to proper voltage levels in order to obtain highest possible noise immunity. to prevent crossconduction of the output stages the tle 4726 uses a special break before make timing of the power transistors. this timing circuit can be triggered by short glitches (some hundred nanoseconds) at the phase inputs causing the output stage to become high resistive during some microseconds. this will lead to a fast current decay during that time. to achieve maximum current accuracy such glitches at the phase inputs should be avoided by proper control signals.
tle 4726 data sheet 22 1999-09-15 thermal shut down to protect the circuit against thermal destruction, thermal shut down has been implemented. to provide a warning in critical applications, the current of the sensing element is wired to input inhibit. before thermal shut down occurs inhibit will start to pull down by some hundred microamperes. this current can be sensed to build a temperature prealarm.
tle 4726 data sheet 23 1999-09-15 package outlines 15.6 -0.4 24 13 112 index marking 1) 1.27 2) 0.35 +0.15 0.2 24x -0.2 2.65 max 0.1 0.2 -0.1 2.45 1) -0.2 7.6 0.35 x 45? 8? max 0.23 +0.09 10.3 0.3 0.4 +0.8 1) does not include plastic or metal protrusions of 0.15 max rer side 2) does not include dambar protrusion of 0.05 max per side gps05144 p-dso-24-3 (plastic dual small outline package) sorts of packing package outlines for tubes, trays etc. are contained in our data book package information. dimensions in mm smd = surface mounted device

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